Static random access memories (SRAMs) are generally used in applications requiring high speed, such as a cache memory in a data processing system. A SRAM is usually implemented as an array of memory cells organized in rows and columns. Each SRAM cell stores one bit of data and is implemented as a pair of inverters having their inputs and outputs cross-coupled at differential storage nodes. The SRAM cell is “bistable”, that is, it is stable at one of two possible logic levels. The logic state of the cell is determined by whichever of the two inverter outputs is a logic high, and can be made to change states by applying a voltage of sufficient magnitude and duration to the appropriate cell input.
Many applications for embedded SRAMs today require the ability to access the memory array while the integrated circuit is operating in a low power mode. However, the static noise margin of a cell decreases as the power supply voltage decreases. If the cell has inadequate noise margins, the logic state that is stored in the cell may be inadvertently changed when the cell is accessed for a read operation. This is commonly referred to as a “read disturb”.
Therefore, what would be desirable is a memory, and a method for operating the memory, that allows operation at lower voltages with adequate static noise margins.